Iron law of processor performance

In computer architecture, the iron law of processor performance (or simply iron law of performance) is a mathematical formulation describing performance trade-offs between complexity and the number of primitive instructions processors use to perform calculations.^[1] This formulation of the problem spurred the development RISC^{[citation needed]} (Reduced Instruction Set Computers) whose instruction set architectures leverage a smaller set of core instructions to improve performance. The term was coined by Douglas Clark^[2] based on research performed by Clark and Joel Emer in the 1980s.^[3]

Explanation[]

The performance of a processor can be summarized as the time it takes to execute a program: ${\displaystyle {\tfrac {Time}{Program}}}$. This can be further broken down into three factors:^[4]

The instruction set architecture impacts ${\displaystyle {\tfrac {Instructions}{Program}}\times {\tfrac {ClockCycles}{Instruction}}}$ as ${\displaystyle {\tfrac {Time}{ClockCycles}}}$ is largely determined by the manufacturing technology. Classic Complex Instruction Set Computer (CISC) ISAs optimized ${\displaystyle {\tfrac {Instructions}{Program}}}$ by providing a larger set of more complex CPU instructions. Generally speaking, however, complex instructions inflate the number clock cycles per instruction (${\displaystyle {\tfrac {ClockCycles}{Instruction}}}$) because they must be decoded into simpler micro-operations correlating to the actual operations performed by the hardware. After converting X86 binary to the micro-operations used internally, the total number of operations is very close to what is produced for a comparable RISC ISA.^[5]

The iron law of processor performance makes this trade-off explicit and pushes for optimization of ${\displaystyle {\tfrac {Time}{Program}}}$as a whole, not just a single sub-component. While the iron law is credited for sparking the development of RISC architectures^{[citation needed]}, it does not imply that a simpler ISA is always faster. If that was the case, the fastest ISA would consist of simple binary logic^{[citation needed]}. A single CISC instruction can be faster than the equivalent set of RISC instructions when it enables multiple consecutive micro-operations to be performed one clock cycle. However, a well designed architecture can achieve the same performance without bloating the core ISA via modular extensions, compressed instructions, and macro-operation fusion.^[6][5][7]

See also[]

• Reduced instruction set computer
• Classic RISC pipeline

References[]