ARM11

ARM11
General information
Designed by	ARM Holdings
Architecture and classification
Microarchitecture	ARMv6, ARMv6T2, ARMv6Z, ARMv6K
Instruction set	ARM (32-bit),; Thumb (16-bit),; Thumb-2 (32-bit)

ARM11 is a group of older 32-bit RISC ARM processor cores licensed by ARM Holdings.^[1] The ARM11 core family consists of ARM1136J(F)-S, ARM1156T2(F)-S, ARM1176JZ(F)-S, and ARM11MPCore. Since ARM11 cores were released from 2002 to 2005, they are no longer recommended for new IC designs, instead ARM Cortex-A and ARM Cortex-R cores are preferred.^[1]

Overview[]

Announced
Year	Core
2002	ARM1136J(F)-S
2003	ARM1156T2(F)-S
2003	ARM1176JZ(F)-S
2005	ARM11MPCore

The ARM11 microarchitecture (announced 29 April 2002) introduced the ARMv6 architectural additions which had been announced in October 2001. These include SIMD media instructions, multiprocessor support and a new cache architecture. The implementation included a significantly improved instruction processing pipeline, compared to previous ARM9 or ARM10 families, and is used in smartphones from Apple, Nokia, and others. The initial ARM11 core (ARM1136) was released to licensees in October 2002.

The ARM11 family are currently the only ARMv6-architecture cores. There are, however, ARMv6-M cores (Cortex-M0 and Cortex-M1), addressing microcontroller applications;^[2] ARM11 cores target more demanding applications.

Differences from ARM9[]

In terms of instruction set, ARM11 builds on the preceding ARM9 generation. It incorporates all ARM926EJ-S features^{[citation needed]} and adds the ARMv6 instructions for media support (SIMD) and accelerating IRQ response.

Microarchitecture improvements in ARM11 cores^[3] include:

SIMD instructions which can double MPEG-4 and audio digital signal processing algorithm speed
Cache is physically addressed, solving many cache aliasing problems and reducing context switch overhead.
Unaligned and mixed-endian data access is supported.
Reduced heat production and lower overheating risk
Redesigned pipeline, supporting faster clock speeds (target up to 1 GHz)
- Longer: 8 (vs 5) stages
- Out-of-order completion for some operations (e.g., stores)
- Dynamic branch prediction/folding (like XScale)
- Cache misses don't block execution of non-dependent instructions.
- Load/store parallelism
- ALU parallelism
64-bit data paths

JTAG debug support (for halting, stepping, breakpoints, and watchpoints) was simplified. The EmbeddedICE module was replaced with an interface which became part of the ARMv7 architecture. The hardware tracing modules (ETM and ETB) are compatible, but updated, versions of those used in the ARM9. In particular, trace semantics were updated to address parallel instruction execution and data transfers.

ARM makes an effort to promote recommended Verilog coding styles and techniques. This ensures semantically rigorous designs, preserving identical semantics throughout the chip design flow, which included extensive use of formal verification techniques. Without such attention, integrating an ARM11 with third-party designs could risk exposing hard-to-find latent bugs. Due to ARM cores being integrated into many different designs, using a variety of logic synthesis tools and chip manufacturing processes, the impact of its register-transfer level (RTL) quality is magnified many times.^[4] The ARM11 generation focused more on synthesis than previous generations, making such concerns more of an issue.