Comparison of ARMv8-A processors

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This is a table of 64/32-bit central processing units which implement the ARMv8-A instruction set architecture and mandatory or optional extensions of it. Most chips support the 32-bit ARMv7-A for legacy applications. All chips of this type have a floating-point unit (FPU) that is better than the one in older ARMv7-A and NEON (SIMD) chips. Some of these chips have coprocessors also include cores from the older 32-bit architecture (ARMv7). Some of the chips are SoCs and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung Exynos 7 Octa.

Table[]

Company Core Released Revision Decode Pipeline
depth 		Out-of-order
execution 		Branch
prediction 		big.LITTLE role Exec.
ports 		SIMD Fab
(in nm) 		Simult. MT L0 cache L1 cache
Instr + Data
(in KiB) 		L2 cache L3 cache Core
configu-
rations 		DMIPS/
MHz[note 1] 		ARM part number (in the main ID register)
Have it Entries
ARM Ltd. Cortex-A32 (32-bit)[1] 2017 ARMv8.0-A
(only 32-bit)		 2-wide 8 No 0 ? LITTLE ? ? 28[2] No No 8–64 + 8–64 0–1 MiB No 1-4+ ? 0xD01
Cortex-A34 (64-bit)[3] 2019 ARMv8.0-A
(only 64-bit)		 2-wide 8 No 0 ? LITTLE ? ? ? No No 8–64 + 8–64 0–1 MiB No 1-4+ ? 0xD02
Cortex-A35[4] 2017 ARMv8.0-A 2-wide[5] 8 No 0 Yes LITTLE ? ? 28 / 16 /
14 / 10		 No No 8–64 + 8–64 0 / 128 KiB–1 MiB No 1–4+ 1.78 0xD04
Cortex-A53[6] 2014 ARMv8.0-A 2-wide 8 No 0 Conditional+
Indirect branch
prediction		 big/LITTLE 2 ? 28 / 20 /
16 / 14 / 10		 No No 8–64 + 8–64 128 KiB–2 MiB No 1–4+ 2.24 0xD03
Cortex-A55[7] 2017 ARMv8.2-A 2-wide 8 No 0 big/LITTLE 2 ? 28 / 20 /
16 / 14 / 12 / 10 / 5[8] 		No No 16–64 + 16–64 0–256 KiB/core 0–4 MiB 1–8+ 2.65[9] 0xD05
Cortex-A57[10] 2013 ARMv8.0-A 3-wide 15 Yes
3-wide dispatch		 ? ? big 8 ? 28 / 20 /
16[11] / 14		 No No 48 + 32 0.5–2 MiB No 1–4+ 4.6 0xD07
[12] 2019 ARMv8.2-A ? ? Yes Two-level ? 2 ? No No ? ? ? ? ? 0xD06
[13] 2019 ARMv8.2-A ? ? Yes Two-level ? 2 ? SMT2 No 16-64 + 16-64 64-256 KiB 0-4 MB 1–8 ? 0xD43
Cortex-A72[14] 2015 ARMv8.0-A 3-wide 15 Yes
5-wide dispatch 		Two-level big 8 28 / 16 No No 48 + 32 0.5–4 MiB No 1–4+ 4.72 0xD08
Cortex-A73[15] 2016 ARMv8.0-A 2-wide 11–12 Yes
4-wide dispatch 		Two-level big 7 28 / 16 / 10 No No 64 + 32/64 1–8 MiB No 1–4+ ~6.35 0xD09
Cortex-A75[7] 2017 ARMv8.2-A 3-wide 11–13 Yes
6-wide dispatch 		Two-level big 8? 2*128b 28 / 16 / 10 No No 64 + 64 256–512 KiB/core 0–4 MiB 1–8+ 8.2-9.5[16] 0xD0A
Cortex-A76[17] 2018 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch 		128 Two-level big 8 2*128b 10 / 7 No No 64 + 64 256–512 KiB/core 1–4 MiB 1–4 10.7-12.4[16] 0xD0B
[18] 2018 ARMv8.2-A ? ? Yes 128 Two-level big ? ? No No ? ? ? ? ? 0xD0E
Cortex-A77[19] 2019 ARMv8.2-A 4-wide 11–13 Yes
10-wide dispatch 		160 Two-level big 12 2*128b 7 No 1.5K entries 64 + 64 256–512 KiB/core 1–4 MiB 1-4 ? 0xD0D
Cortex-A78[20][21] 2020 ARMv8.2-A 4-wide Yes 160 Yes big 13 2*128b No 1.5K entries 32/64 + 32/64 256–512 KiB/core 1–4 MiB 1-4 ? 0xD41
Cortex-X1[22] 2020 ARMv8.2-A 5-wide[22] ? Yes 224 Yes big 15 4*128b No 3K entries 64 + 64 up to 1 MiB[22] up to 8 MiB[22] custom[22] ? 0xD44
Apple Inc. Cyclone[23] 2013 ARMv8.0-A 6-wide[24] 16[24] Yes[24] 192 Yes No 9[24] 28[25] No No 64 + 64[24] 1 MiB[24] 4 MiB[24] 2[26] 1.3-1.4 GHz
Typhoon 2014 ARMv8.0‑A 6-wide[27] 16[27] Yes[27] Yes No 9 20 No No 64 + 64[24] 1 MiB[27] 4 MiB[24] 2, 3 (A8X) 1.1-1.5 GHz
Twister 2015 ARMv8.0‑A 6-wide[27] 16[27] Yes[27] Yes No 9 16 / 14 No No 64 + 64[27] 3 MiB[27] 4 MiB[27]
No (A9X)		 2 1.85-2.26 GHz
Hurricane 2016 ARMv8.0‑A 6-wide[28] 16 Yes "big" (In A10/A10X paired with "LITTLE" Zephyr
cores) 		9 3*128b 16 (A10)
10 (A10X) 		No No 64 + 64[29] 3 MiB[29] (A10)
8 MiB (A10X) 		4 MiB[29] (A10)
No (A10X) 		2x Hurricane (A10)
3x Hurricane (A10X) 		2.34-2.36 GHz
Zephyr ARMv8.0‑A 3-wide 12 Yes LITTLE 5 16 (A10)
10 (A10X) 		No No 32 + 32[30] 1 MiB 4 MiB[29] (A10)
No (A10X) 		2x Zephyr (A10)
3x Zephyr (A10X) 		1.09-1.3 GHz
Monsoon 2017 ARMv8.2‑A[31] 7-wide 16 Yes "big" (In Apple A11 paired with "LITTLE" Mistral
cores) 		11 3*128b 10 No No 64 + 64[30] 8 MiB No 2x Monsoon 2.39 GHz
Mistral ARMv8.2‑A[31] 3-wide 12 Yes LITTLE 5 10 No No 32 + 32[30] 1 MiB No 4× Mistral 1.19 GHz
Vortex 2018 ARMv8.3‑A[32] 7-wide 16 Yes "big" (In Apple A12/Apple A12X/Apple A12Z paired with "LITTLE" Tempest
cores) 		11 3*128b 7 No No 128 + 128[30] 8 MiB No 2x Vortex (A12)
4x Vortex (A12X/A12Z) 		2.49 GHz
Tempest ARMv8.3‑A[32] 3-wide 12 Yes LITTLE 5 7 No No 32 + 32[30] 2 MiB No 4x Tempest 1.59 GHz
Lightning 2019 ARMv8.4‑A [33] 8-wide 16 Yes 560 "big" (In Apple A13 paired with "LITTLE" Thunder
cores) 		11 3*128b 7 No No 128 + 128[34] 8 MiB No 2x Lightning 2.65 GHz
Thunder ARMv8.4‑A [33] 3-wide 12 Yes LITTLE 5 7 No No 96 + 48[35] 4 MiB No 4x Thunder 1.8 GHz
Firestorm 2020 ARMv8.4-A[citation needed] 8-wide[36] Yes 630[37] "big" (In Apple A14 and Apple M1/M1 Pro/M1 Max/M1 Ultra paired with "LITTLE" Icestorm
cores) 		14 4*128b 5 No 192 + 128 8 MiB (A14)
12 MiB (M1)
24 MiB (M1 Pro/M1 Max)
48 MiB (M1 Ultra) 		No 2x Firestorm (A14)
4x Firestorm (M1)

6x or 8x Firestorm (M1 Pro)
8x Firestorm (M1 Max)
16x Firestorm (M1 Ultra)

3.0-3.23 GHz
Icestorm ARMv8.4[citation needed] 4-wide Yes 110 LITTLE 7 2*128b 5 No 128 + 64 4 MiB
8 MiB (M1 Ultra) 		No 4x Icestorm (A14/M1)
2x Icestorm (M1 Pro/Max)
4x Icestorm (M1 Ultra) 		1.82-2.06 GHz
Avalanche 2021 ARMv8.5‑A[citation needed] 8-wide Yes "big" (In Apple A15 paired with "LITTLE" Blizzard
cores) 		14 4*128b 5 No 192 + 128 12 MiB No 2x Avalanche 2.93-3.23 GHz
Blizzard ARMv8.5‑A[citation needed] 4-wide Yes LITTLE 8 2*128b 5 No 128 + 64 4 MiB No 4x Blizzard 2.02 GHz
Nvidia Denver[38][39] 2014 ARMv8‑A 2-wide hardware
decoder, up to
7-wide variable-
length VLIW
micro-ops 		13 Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW. 		Direct+
Indirect branch
prediction 		No 7 28 No No 128 + 64 2 MiB No 2 ?
Denver 2[40] 2016 ARMv8‑A ? 13 Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW. 		Direct+
Indirect branch
prediction 		"Super" Nvidia's own implementation ? 16 No No 128 + 64 2 MiB No 2 ?
Carmel 2018 ARMv8.2‑A ? Direct+
Indirect branch
prediction 		? 12 No No 128 + 64 2 MiB (4 MiB @ 8 cores) 2 (+ 8) ?
Cavium ThunderX[41][42] 2014 ARMv8-A 2-wide 9[42] Yes[41] Two-level ? 28 No No 78 + 32[43][44] 16 MiB[43][44] No 8–16, 24–48 ?
ThunderX2
[45](ex. Broadcom Vulcan[46]) 		2018[47] ARMv8.1-A
[48]		 4-wide
"4 μops"[49][50]		 ? Yes[51] Multi-level ? ? 16[52] SMT4 No 32 + 32
(data 8-way)		 256 KiB
per core[53]		 1 MiB
per core[53]		 16-32[53] ?
Marvell 2020[54] ARMv8.3+[54] 8-wide ? Yes
4-wide dispatch 		Multi-level ? 7 7[54] SMT4[54] ? 64 + 32 512 KiB
per core		 90 MiB 60 ?
Applied

Micro

Helix 2014 ? ? ? ? ? ? ? 40 / 28 No No 32 + 32 (per core;
write-through
w/parity)[55]		 256 KiB shared
per core pair (with ECC)		 1 MiB/core 2, 4, 8 ?
X-Gene 2013 ? 4-wide 15 Yes ? ? ? 40[56] No No 8 MiB 8 4.2
X-Gene 2 2015 ? 4-wide 15 Yes ? ? ? 28[57] No No 8 MiB 8 4.2
X-Gene 3[57] 2017 ? ? ? ? ? ? ? 16 No No ? ? 32 MiB 32 ?
Qualcomm Kryo 2015 ARMv8-A ? ? Yes Two-level? "big" or "LITTLE"
Qualcomm's own similar implementation		 ? 14[58] No No 32+24[59] 0.5–1 MiB 2+2 6.3
Kryo 200 2016 ARMv8-A 2-wide 11–12 Yes
7-wide dispatch 		Two-level big 7 14 / 11 / 10 / 6 [60] No No 64 + 32/64? 512 KiB/Gold Core No 4 1.8-2.45 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 2 8–64? + 8–64? 256 KiB/Silver Core 4 1.8-1.9 GHz
Kryo 300 2017 ARMv8.2-A 3-wide 11–13 Yes
8-wide dispatch 		Two-level big 8 10[60] No No 64+64[60] 256 KiB/Gold Core 2 MiB 2, 4 2.0-2.95 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 28 16–64? + 16–64? 128 KiB/Silver 4, 6 1.7-1.8 GHz
Kryo 400 2018 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch 		Yes big 8 11 / 8 / 7 No No 64 + 64 512 KiB/Gold Prime

256 KiB/Gold

2 MiB 2, 1+1, 4, 1+3 2.0-2.96 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 2 16–64? + 16–64? 128 KiB/Silver 4, 6 1.7-1.8 GHz
Kryo 500 2019 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch 		Yes big 8 / 7 No ? 512 KiB/Gold Prime

256 KiB/Gold

3 MiB 2, 1+3 2.0-3.2 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 2 ? 128 KiB/Silver 4, 6 1.7-1.8 GHz
Kryo 600 2020 ARMv8.4-A 4-wide 11–13 Yes
8-wide dispatch 		Yes big 6 / 5 No ? 64 + 64 1024 KiB/Gold Prime

512 KiB/Gold

4 MiB 2, 1+3 2.2-3.0 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 2 ? 128 KiB/Silver 4, 6 1.7-1.8 GHz
Falkor[61][62] 2017[63] "ARMv8.1-A features";[62] AArch64 only (not 32-bit)[62] 4-wide 10–15 Yes
8-wide dispatch 		Yes ? 8 10 No 24 KiB 88[62] + 32 500KiB 1.25MiB 40-48 ?
Samsung M1[64][65] 2016 ARMv8-A 4-wide 13[66] Yes
9-wide dispatch[67] 		96 big 8 14 No No 64 + 32 2 MiB[68] No 4 2.6 GHz
M2[64][65] 2017 ARMv8-A 4-wide 100 Two-level big 10 No No 64 + 64 2 MiB No 4 2.3 GHz
M3[66][69] 2018 ARMv8.2-A 6-wide 15 Yes
12-wide dispatch 		228 Two-level big 12 10 No No 64 + 64 512 KiB per core 4096KB 4 2.7 GHz
M4[70] 2019 ARMv8.2-A 6-wide 15 Yes
12-wide dispatch 		228 Two-level big 12 8 / 7 No No 64 + 64 512 KiB per core 3072KB 2 2.73 GHz
M5[71] 2020 ARMv8.2-A 6-wide Yes
12-wide dispatch 		228 Two-level big 7 No No 64 + 64 512 KiB per core 3072KB 2 2.73 GHz
Fujitsu A64FX[72][73] 2019 ARMv8.2-A 4/2-wide 7+ Yes
5-way? 		Yes n/a 8+ 2*512b[74] 7 No No 64 + 64 8MiB per 12+1 cores No 48+4 1.9 GHz+; 15GF/W+.
HiSilicon TaiShan V110[75] 2019 ARMv8.2-A 4-wide ? Yes n/a 8 7 No No 64 + 64 512 KiB per core 1 MiB per core ? ?
Company Core Released Revision Decode Pipeline
depth 		Out-of-order
execution 		Branch
prediction 		big.LITTLE role Exec.
ports 		SIMD Fab
(in nm) 		Simult. MT L0 cache L1 cache
Instr + Data
(in KiB) 		L2 cache L3 cache Core
configu-
rations 		DMIPS/
MHz 		ARM part number (in the main ID register)

See also[]

Notes[]

  1. ^ As Dhrystone (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution.

References[]

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