Application-specific instruction set processor
 | This article includes a list of references, related reading or external links, but its sources remain unclear because it lacks inline citations. (January 2015) |
An application-specific instruction set processor (ASIP) is a component used in system-on-a-chip design. The instruction set of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose CPU and the performance of an ASIC.
Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: static logic which defines a minimum ISA (instruction-set architecture) and configurable logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to an field-programmable gate array (FPGA) or during the chip synthesis.
ASIPs can be used as an alternative of hardware accelerators for baseband signal processing[1] or video coding.[2] Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten finite-state machines (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.[3] There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).
See also[]
- Application-specific integrated circuit
- System on Chip
- Digital signal processor
References[]
- ^ Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014.
- ^ Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014
- ^ Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006
Literature[]
- Dake Liu (2008). Embedded DSP Processor Design: Application Specific Instruction Set Processors. MA: Elsevier Mogan Kaufmann. ISBN 978-0-12-374123-3.
- Oliver Schliebusch; Heinrich Meyr; Rainer Leupers (2007). Optimized ASIP Synthesis from Architecture Description Language Models. Dordrecht: Springer. ISBN 978-1-4020-5685-7.
- Paolo Ienne, Rainer Leupers (eds.) (2006). Customizable Embedded Processors. San Mateo, CA: Morgan Kaufmann. ISBN 978-0-12-369526-0.CS1 maint: extra text: authors list (link)
- Matthias Gries, Kurt Keutzer (eds.) (2005). Building ASIPs: The Mescal Methodology. New York: Springer. ISBN 978-0-387-26057-0.CS1 maint: extra text: authors list (link)
External links[]
- ASIP Designer, proprietary tool suite from Synopsys enabling compiler-in-the-loop incremental design of ASIPs
- Codasip Studio, proprietary tool suite from Codasip enabling design of ASIPs using CodAL processor description language
- TTA-Based Codesign Environment (TCE), an open source (MIT licensed) toolset for design of application specific TTA processors.
 | This computer hardware article is a stub. You can help Wikipedia by . |
- Application-specific integrated circuits
- Coprocessors
- Gate arrays
- Instruction processing
- Integrated circuits
- Computer hardware stubs