Tremont (microarchitecture)

Tremont
General information
Product code	80691 (Lakefield); 80697 (Jasper Lake)
Architecture and classification
Architecture	Tremont x86
Instructions	x86-64, Intel 64
Extensions	MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2; AES-NI, RDRAND, CLMUL, SHA; VT-x, VT-d;
Physical specifications
Transistors	10 nm transistors;
Cores	4–24;
Products, models, variants
Model(s)	Pentium; Celeron; Atom;
History
Predecessor	Goldmont Plus
Successor	Gracemont

Tremont is a microarchitecture for low-power Atom, Celeron and Pentium Silver branded processors used in systems on a chip (SoCs) made by Intel, it is the successor to Goldmont Plus.^[2] Intel officially launched Elkhart Lake platform with 10nm Tremont core on September 23, 2020.^[3] Intel officially launched Jasper Lake platform with 10nm Tremont core on January 11, 2021.^[4]

Design[]

Tremont is 3rd generation out-of-order low-power Atom microarchitecture designed for the entry level desktop and notebook computers. Tremont is built on the 10 nm manufacturing process and supports up to 24 cores.^[5] It includes the Intel Gen11 graphics architecture from Ice Lake.

Tremont microarchitecture provides the following enhancements over Goldmont Plus:

Enhanced branch prediction unit.
- Increased capacity with improved path-based conditional and indirect prediction.
- New committed Return Stack Buffer.
Novel clustered 6-wide out-of-order front-end fetch and decode pipeline.
- Banked ICache with dual 16B reads.
- Two 3-wide decode clusters enabling up to 6 instructions per cycle.
Deeper back-end out-of-order windows.
32 KB^[a] data cache.
Larger load and store buffers.
Dual generic load and store execution pipes capable of 2 loads, 2 stores, or 1 load and 1 store per cycle.
Dedicated integer and vector integer/floating point store data ports.
New and improved cryptography.
- New Galois-field instructions (GFNI).
- Dual AES units.
- Enhanced SHA-NI implementation.
- Faster PCLMULQDQ.
Support for user level low-power and low-latency spin-loop instructions UMWAIT/UMONITOR and TPAUSE.

Technology[]

10 nm manufacturing process
SoC (System on a chip) architecture
3D tri-gate transistors
32 KB^[a] L1 data cache, up from 24 KB in Goldmont Plus
1.5 MB - 4.5 MB shared L2 cache per 4-core cluster, up from 4 MB in Goldmont Plus
4 MB shared L3 cache
Gen 11 GPU^[6]^[7] with DirectX 12, OpenGL 4.6, Vulkan 1.2, OpenGL ES 3.2 and OpenCL 3.0 support.
10 W thermal design power (TDP) desktop processors
6 W TDP mobile processors

List of Tremont processors[]

Mobile processors (Jasper Lake)[]

List of mobile processors as follows:^[8]

Target segment	Cores (Threads)	Processor Branding & Model		GPU Model		TDP	SDP	CPU Clock rate		Graphics Clock rate		L2 Cache [MB]	L3 Cache [MB]	Release Date	Price (USD)
Target segment	Cores (Threads)	Processor Branding & Model		GPU Model		TDP	SDP	Base	Turbo	Normal	Turbo	L2 Cache [MB]	L3 Cache [MB]	Release Date	Price (USD)
Mobile	4 (4)	Pentium Silver	N6005	UHD Graphics	32 EU	10 W	-	2.0 GHz	3.3 GHz	450 MHz	900 MHz	1.5 MB	4 MB	Q1 2021
		Pentium Silver	N6000		32 EU	6 W	4.8 W	1.1 GHz	3.3 GHz	350 MHz	850 MHz
		Celeron	N5105		24 EU	10 W	-	2.0 GHz	2.9 GHz	450 MHz	800 MHz
			N5100		24 EU	6 W	4.8 W	1.1 GHz	2.8 GHz	350 MHz	800 MHz
	2 (2)		N4505		16 EU	10 W	-	2.0 GHz	2.9 GHz	450 MHz	750 MHz
	2 (2)		N4500		16 EU	6 W	4.8 W	1.1 GHz	2.8 GHz	350 MHz	750 MHz

Mobile processors (Lakefield)[]

Pentacore Lakefield CPU consists of 1 "big" Sunny Cove core and 4 "little" Tremont cores. AVX support on Sunny Cove (still physically present) is disabled to match Tremont core.

Target segment	Cores (Threads)	Processor Branding & Model		GPU Model		TDP	CPU Clock rate		Graphics Clock rate		L2 Cache [MB]	Release Date	Price (USD)
Target segment	Cores (Threads)	Processor Branding & Model		GPU Model		TDP	Base	Turbo	Normal	Turbo	L2 Cache [MB]	Release Date	Price (USD)
Mobile	1+4 (5)	Core i5	L16G7	UHD Graphics	64 EU	7 W	1.4 GHz	3.0 GHz	200 MHz	500 MHz	1.5 + 4 (L3)	Q2 2020	$281
Mobile	1+4 (5)	Core i3	L13G4	UHD Graphics	48 EU	7 W	0.8 GHz	2.8 GHz	200 MHz	500 MHz	1.5 + 4 (L3)	Q2 2020	$281

Processors for base transceiver stations ()[]

Target segment	Cores (Threads)	Processor Branding & Model		TDP	CPU Clock rate	L2 Cache [MB]	Release Date	Price (USD)
Target segment	Cores (Threads)	Processor Branding & Model		TDP	Base	L2 Cache [MB]	Release Date	Price (USD)
Server	8 (8)	Atom P	P5921B	Not disclosed	2.2 GHz	9	Q1 2020	Not disclosed. These processors are exclusively produced for cell phone radio manufacturers.
	12 (12)		P5931B			13.5
	16 (16)		P5942B			18
	24 (24)		P5962B			27

Source: Intel Atom® Processor P Series Product Specifications

Embedded processors (Elkhart Lake)[]

List of embedded processors as follows:^[9]

Target segment	Cores (Threads)	Processor Branding & Model		GPU model		TDP	CPU Clock rate		Graphics Clock rate		L2cache [MB]	Memory	Release date	Release price (USD)
Target segment	Cores (Threads)	Processor Branding & Model		GPU model		TDP	Base	Turbo	Base	Turbo	L2cache [MB]	Memory	Release date	Release price (USD)
Embedded	4 (4)	Pentium	J6425	UHD Graphics	32 EU	10 W	1.8 GHz	3.0 GHz	400 MHz	850 MHz	1.5 MB	4 × LPDDR4X-4267 2 × DDR4-3200	Q1 2021
		Pentium	N6415		16 EU	6.5 W	1.2 GHz		350 MHz	800 MHz
		Celeron	J6413			10 W	1.8 GHz		400 MHz	800 MHz
	2 (2)	Celeron	N6211			6.5 W	1.2 GHz		250 MHz	750 MHz
	4 (4)	Atom	x6425RE		32 EU	12 W	1.9 GHz	N/A	400 MHz	N/A
			x6427FE				1.9 GHz	N/A	400 MHz	N/A
			x6425E				1.8 GHz	3.0 GHz	500 MHz	750 MHz
			x6413E		16 EU	9 W	1.5 GHz	3.0 GHz	500 MHz	750 MHz
			x6414RE			9 W	1.5 GHz	N/A	400 MHz	N/A
	2 (2)		x6212RE			6 W	1.2 GHz	N/A	350 MHz	N/A
			x6211E			6 W	1.2 GHz	3.0 GHz	350 MHz	750 MHz
			x6200FE	N/A		4.5 W	1.0 GHz	N/A			1 MB

Notes[]

^ ^a ^b Transistorized memory, such as RAM, ROM, flash and cache sizes as well as file sizes are specified using binary meanings for K (1024¹), M (1024²), G (1024³), etc.

References[]

^ "Gracemont". Gracemont - Microarchitectures - Intel. WikiChip.org. Retrieved 29 March 2020.
^ "Intel Introduces Tremont Microarchitecture". Intel Newsroom.
^ "IoT-Enhanced Processors Increase Performance, AI, Security".
^ "CES 2021: Intel Announces Four New Processor Families".
^ Cutress, Dr Ian. "Intel's new Atom Microarchitecture: The Tremont Core in Lakefield". AnandTech. Retrieved 2019-10-24.
^ https://software.intel.com/sites/default/files/managed/db/88/The-Architecture-of-Intel-Processor-Graphics-Gen11_R1new.pdf
^ "Developer and Optimization Guide for Intel® Processor Graphics Gen11 API". software.intel.com. November 25, 2019.
^ Cite error: The named reference jasper was invoked but never defined (see the help page).
^ "Products formerly Elkhart Lake".

[prefix-6] Transistorized memory, such as RAM, ROM, flash and cache sizes as well as file sizes are specified using binary meanings for K (1024¹), M (1024²), G (1024³), etc.

[1] "Gracemont". Gracemont - Microarchitectures - Intel. WikiChip.org. Retrieved 29 March 2020.

[2] "Intel Introduces Tremont Microarchitecture". Intel Newsroom.

[3] "IoT-Enhanced Processors Increase Performance, AI, Security".

[4] "CES 2021: Intel Announces Four New Processor Families".

[the-tremont-core-5] Cutress, Dr Ian. "Intel's new Atom Microarchitecture: The Tremont Core in Lakefield". AnandTech. Retrieved 2019-10-24.

[7] ttps://software.intel.com/sites/default/files/managed/db/88/The-Architecture-of-Intel-Processor-Graphics-Gen11_R1new.pdf

[8] "Developer and Optimization Guide for Intel® Processor Graphics Gen11 API". software.intel.com. November 25, 2019.

[jasper-9] Cite error: The named reference jasper was invoked but never defined (see the help page).

[10] "Products formerly Elkhart Lake".

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