180 nm process

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The 180 nm process refers to the level of MOSFET (CMOS) semiconductor process technology that was commercialized around the 1998–2000 timeframe by leading semiconductor companies, starting with TSMC[1] and Fujitsu,[2] then followed by Sony, Toshiba,[3] Intel, AMD, Texas Instruments and IBM.

The origin of the 180 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years.[citation needed] The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).

Some of the first CPUs manufactured with this process include Intel Coppermine family of Pentium III processors. This was the first technology using a gate length shorter than that of light used for contemporary lithography, which had a minimum feature size of 193 nm.[citation needed]

Some more recent[when?] microprocessors and microcontrollers (e.g. PIC) are using this technology because it is typically low cost and does not require upgrading of existing equipment.[citation needed]

History[]

In 1988, an IBM research team led by Iranian engineer Bijan Davari fabricated a 180 nm dual-gate MOSFET using a CMOS process.[4] The 180 nm CMOS process was later commercialized by TSMC in 1998,[1] and then Fujitsu in 1999.[2]

Processors using 180 nm manufacturing technology[]

  • Intel Coppermine E—October 1999
  • ATI Radeon R100 and RV100 Radeon 7000—2000
  • Nintendo GameCube's Gekko CPU—2000
  • Sony PlayStation 2's Emotion Engine and Graphics Synthesizer—March 2000[3]
  • AMD Athlon Thunderbird—June 2000
  • AMD Duron Spitfire–June 2000
  • AMD Duron Morgan–August 2001
  • Intel Celeron (Willamette)—May 2002
  • Motorola PowerPC 7445 and 7455 (Apollo 6)—January 2002

References[]

  1. ^ Jump up to: a b "0.18-micron Technology". TSMC. Retrieved 30 June 2019.
  2. ^ Jump up to: a b 65nm CMOS Process Technology
  3. ^ Jump up to: a b "EMOTION ENGINE® AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION® BECOME ONE CHIP" (PDF). Sony. April 21, 2003. Retrieved 26 June 2019.
  4. ^ Davari, Bijan; et al. (1988). "A high-performance 0.25 micrometer CMOS technology". International Electron Devices Meeting. doi:10.1109/IEDM.1988.32749. S2CID 114078857.
Preceded by
250 nm
CMOS manufacturing processes Succeeded by
130 nm
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